Research on Circuit Level Protection Design of SRAM Single Event Latch-up Effect

Abstract

SRAM with high density CMOS technology is extremely sensitive to single event latch�up, so it is necessary to adopt corresponding protection strategies in space applications. For CTOS with reduced radiation resistance, circuit level protection becomes an important part to improve system reliability. A series of single event latch�up effect tests were carried out on CY62167DV30LL SRAM of CYPRESS Company by using laser single event effect test device. Through the linear fitting of the experimental results, the holding voltage of the SRAM is 1�5�1�6 V, and the holding current is 9�9�11�2 mA. According to the holding current, holding voltage, working current and working voltage, judge whether circuit level protection can be adopted. Two circuit level protection methods of power supply current limiting and divider resistor were proposed, and the value range of power supply current limiting and divider resistor were calculated quantitatively. In the previous literature, resistor is only used as a means of current limiting after latch�up trigger, which can not prevent the device from latch�up. It is found that the divider resistor can also achieve the purpose of preventing the latch�up under certain conditions. The two protection methods were verified by pulse laser test.

Keywords

• single event latch-up
• static random access memory
• pulse laser
• circuit level protection