Proposal of Global Strain Clocking Scheme for Majority Logic Gate

Abstract

A stairs-type global strain clocking mechanism for nanomagnetic majority logic gate based on shape engineering of nanomagnets was designed in this paper. Reasonable size nanomagnets and proper strain clocking scheme ensure the computing architecture pipelined at room temperature. The optimal global strain clocking scheme was obtained by investigating the impact of magnetic layer thickness and width on clocking period and strain magnitude. Encouragingly, for the global strain clocking, information transmission speed of majority logic gate is increased 1-2 times as against the local strain clocking scheme due to decreasing the number of start-ups during information transmission. While the energy dissipated per clock cycle of the global strain clocking scheme consumes 3-4 times less energy than that of local strain clocking scheme. Moreover, global clocking is used to control a nanomagnetic logic device(NMLD), in which case single device consisted of many nanomagnets can be treated as single nanomagnet. However, magnetization switching is error-prone in the presence of thermal noise at room temperature. Therefore, the proper structure parameters of the device are obtained at room temperature, in which case the error probability of the majority logic gate is 0.5% in theoretical simulation. These results provide essential guidance for the design of energy-efficient multiferroic nanomagnetic logic devices.

Keywords

• Energy-efficient
• global strain clocking
• nanomagnetic logic device (NMLD)
• shape engineering
• spintronics