A memory reduced Turbo code decoding architecture design and FPGA implementation

Abstract

In order to satisfy the high-performance and low-power dissipation requirement in wireless communication, this paper proposes a low storage capacity and low-power dissipation Turbo decoder architecture based on the reverse recalculation and linear estimation by changing the storage method of the forward state metric, while the FPGA implementation structure is given. The results show that compared with the existing Turbo code decoder, the decoding structure designed in this paper reduces the storage capacity to 65%, and the decoding performance is close to the Log-MAP algorithm. In particular, compared with the traditional decoder architecture, dynamic storage capacity power dissipation is reduced by about 50%, and the overall power dissipation of the decoder architecture is decreased by 4.97%, 8.78%, 11.93%, 14.18% and 14.65% at the frequency of 25 MHz,50 MHz,75 MHz,100 MHz and 125 MHz, respectively.

Keywords

• low-power dissipation
• wireless communication
• turbo code
• fpga implementation
• log-map algorithm