Impact of JFET Region Width on Single Event Effects of SiC MOSFETs

Abstract

The advantages of SiC MOSFETs (metal-oxide semiconductor field effect transistor) make this technology attractive for space, avionics and high-energy accelerator applications. However, the current commercial technologies are still susceptible to single event effects (SEEs) and latent damages induced by the radiation environment. In commercial SiC MOSFETs exposed to heavy ions, two types of latent damages were experimentally observed. One type is observed at bias voltages just below the degradation onset voltage and involves the gate oxide. The other type of damage was observed at bias voltages below the single event burnout (SEB) limit and which was attributed to changes in the silicon carbide lattice. The key parameter of SiC MOSFET, JFET region width, has been considered as the main influence factor of SEEs of SiC MOSFET. Aiming at this influence factor, SEE experiment was carried out on 12 kV SiC MOSFET devices with different JFET region widths of the same structure to investigate the influence of different JFET region widths on the device’s SEEs burning threshold voltage, leakage degradation threshold voltage, and the device performance under negative gate voltage conditions, and the test results show that the leakage degradation threshold voltage increases with the decrease of the JFET region width. Reducing the JFET region width of the device can effectively improve the SEEs resistance of the device, this effect is also observed under negative gate voltage bias conditions. Under negative gate voltage bias conditions, the effect of JFET region width on the SEEs of the device is reduced by the negative gate voltage. Sentaurus TCAD is used for simulation, and the simulation results confirm that the JFET region width and the negative gate voltage bias affect the accumulation of holes in the JFET region under the oxide layer, which in turn affects the oxide layer field strength, and thus affects the single event leakage degradation of the device. It is also demonstrated that SEB is caused by a localized energy pulse due to ion collisional ionization, followed by avalanche multiplication, which generates a large amount of Joule heat and leads to permanent structural damage in the device. The whole burn-in process does not correlate well with the JFET region width, and all changes in the JFET region width do not have a significant effect on the burn-in voltage, which is in line with the experimental results. The JFET region width is only one of the factors affecting the single event leakage degradation effect. The in-depth research will be carried out, with the help of advanced TCAD software to find out the intrinsic mechanism causing this phenomenon, in order to provide technological support for the radiation hardening of SiC power devices.

Keywords

• sic
• leakage degradation
• single event effect
• radiation resistance