Analysis and Design of Noise-Shaping SAR ADC with Capacitor Stacking and Buffering
Zhaoyang Shen,
Shiheng Yang,
Jiaxin Liu
Affiliations
Zhaoyang Shen
School of Intergrated Circuit Science and Engineering (Exemplary School of Microelectronics), University of Electronic Science and Technology of China (UESTC), Chengdu 611731, China
Shiheng Yang
School of Intergrated Circuit Science and Engineering (Exemplary School of Microelectronics), University of Electronic Science and Technology of China (UESTC), Chengdu 611731, China
Jiaxin Liu
School of Intergrated Circuit Science and Engineering (Exemplary School of Microelectronics), University of Electronic Science and Technology of China (UESTC), Chengdu 611731, China
The noise-shaping (NS) successive-approximation-register (SAR) is a promising analog-to-digital converter (ADC) architecture which combines the benefits of SAR and Delta-Sigma (ΔΣ) ADCs. Among the various NS-SAR approaches, the recent emerged one with capacitor stacking and buffering exhibits excellent energy efficiency. This paper presents a tutorial for the design of NS-SAR ADC with capacitor stacking and buffering. The fundamental principle of the NS-SAR loop filter is analyzed, an ADC design example is provided, and the circuit implementation details with considerations on the non-idealities and trade-offs are discussed. This paper can be used as a tutorial for designing high-resolution and high-order NS-SAR ADC.
