FPGA Implementation of Variable Step Power Inversion Array for BeiDou Receiver

Abstract

Given the susceptibility of satellite signals to intentional or unintentional interference; it is imperative to incorporate hardware-based navigation anti-jamming algorithms. Currently, spatial domain filtering is widely applied. While numerous variable step size (VSS) algorithms were used to improve the performance, most of these are either computationally complex or depend on many parameters that are hard to tune manually. Some algorithms might improve one index but worsen overall performance, making them unreliable in practical scenarios. To address these challenges, we propose a novel variable step power inversion (PI) that involves just one adaptive parameter. By establishing a new non-linear function model between step size and system output, the parameter can be adapted based on the output. Meanwhile, a variable step PI that can be easily implemented by field programmable gate array (FPGA) is proposed, thereby achieving a balance between accuracy and iteration speed. The proposed algorithm can converge within 10 iterations, effectively suppressing individual interference below −300dB. In comparison to existing algorithms, the proposed algorithm is characterized by swift convergence, high convergence accuracy, low complexity, and robust anti-jamming capabilities. Finally, FPGA hardware testing is conducted, and the experimental and simulation results are in good agreement, affirming anti-jamming capabilities.

Keywords

• Power inversion array
• variable step size (VSS)
• navigation anti-jamming
• FPGA