Iterative Placement of Decoupling Capacitors using Optimization Algorithms and Machine Learning

Abstract

In this work, an approach for optimum placement of on-board decoupling capacitors (decaps) is presented, which aims at reducing transient noise in power delivery networks (PDNs). This approach is based on a genetic algorithm (GA) and accelerated by the use of an artificial neural network (ANN) as surrogate model to efficiently determine the fitness of a decap design, i.e., of a particular choice for the position and the type of the decaps to integrate in the printed circuit board (PCB). The ANN is trained by a suitable set of reference designs labeled by the impedance at the power pin of the integrated circuit (IC), which is computed by commercial simulation software. Several iterative runs of the GA are performed with an increasing number of decaps to identify a design with the least number of decaps necessary to reduce the distance of the frequency domain input impedance of the considered point-to-point connection from a desired target impedance as far as possible. This approach is successfully applied to generate an optimum decap design for a PDN with 52 possible decap positions and decaps chosen from three types.