Design of LBT transform controller based on FPGA′s timing structure

Abstract

For the lapped bi-orthogonal transform(LBT) in JPEG XR encoding algorithm, the traditional implement method is always using linear lift structure which has no timing constraint, and it could cause some problems such as metastable state, uncontrolled code flow. Therefore, a LBT transform controller based on FPGA′s timing structure has been designed. In this design, mixed state machines is used to make the LBT transform operators to be data dealing modules that are timing-controlling-structure. The data dealing modules communicates with front and back controlling modules through handshake signals, and processes data according to relevant instructions. Single RAM cycle structure is used in the design, so that it can save FPGA internal storage space. The channels between each controlling modules and RAM are switched via channel chooser. Each controlling module computes addresses of image data in real time and reads or writes the RAM crossways on the basis of the feedback instructions of data dealing modules. Experimental results show that the controller has realized FPGA timing constraint on LBT transform, and the images processed by it are almost same to the results on MATLAB. This design has achieved desired goals.

Keywords

• JPEG XR
• LBT
• FPGA
• mixed state machine
• cycle structure