Variance Reduction during the Fabrication of Sub-20 nm Si Cylindrical Nanopillars for Vertical Gate-All-Around Metal-Oxide-Semiconductor Field-Effect Transistors

• Shujun Ye,
• Kikuo Yamabe,
• Tetsuo Endoh

Affiliations

Shujun Ye

†Center for Innovative Integrated Electronic Systems, Tohoku University, Sendai, Japan

Kikuo Yamabe

†Center for Innovative Integrated Electronic Systems, Tohoku University, Sendai, Japan

Tetsuo Endoh

†Center for Innovative Integrated Electronic Systems, Tohoku University, Sendai, Japan