A 4 Gb/s Multi-Dot PIN-Photodiode-Based CMOS Optical Receiver Using a Single to Differential TIA-Equalizer

Abstract

This paper outlines the development of an optical receiver capable of handling data at a rate of 4 Gb/s. The receiver makes use of a multi-dot PIN CMOS photodiode with a bandwidth of 930 MHz (capacitance of 48.8fF) and a responsivity of 0.294 A/W at a wavelength of 675 nm. It also features a single-to-differential (SDT) noise-suppressed transimpedance amplifier (TIA) equalizer. By implementing a low-frequency zero synthesis within the STD-TIA feedback path, the 3-dB frequency roll-off of the photodiode is extended by a factor of 2.63, resulting in an overall front-end bandwidth of 2.45 GHz with a transimpedance gain of 84 dB $\Omega $ . The SDT TIA eliminates the need for a dummy TIA, improving the noise performance of the receiver achieving the integrated input-referred current noise for the entire front-end to less than 717 nA rms. Additionally, a detailed theoretical analysis of equalization methods, as well as the impact of inter-symbol interference (ISI) and noise on bit error rate (BER) degradation is presented. The receiver has been successfully tested for data transmission at rates of 4 Gb/s, 3 Gb/s, and 2.5 Gb/s, achieving bit-error ratios of less than $10^{-9}$ at minimum average optical powers of -16.2 dBm, -17.2 dBm, and -18 dBm, respectively. Furthermore, the receiver consumes 28 mA from a 3.3V power supply and occupies a core area of 1.4 mm $\times 0.7$ mm.

Keywords

• Analog equalizer
• CMOS optical receiver
• intersymbol interference
• noise-suppressed transimpedance amplifier
• optoelectronic integrated circuit
• PIN photodiode