Timing logic analyzer implemented in reprogrammable digital architecture

Abstract

The conception, design, simulation, and implementation of a timing logic analyzer implemented on a reprogrammable digital architecture are described in this paper. The system was specified in VHDL [1] and implemented in a platform based on a FPGA (Field Programmable Gate Array) Spartan II. This methodology for analyzer implementation, allows obtaining a flexible, economic an efficient system in regards to processing capacity, since its modular characteristics make possible, through the use several of the developed subsystems, to scale the system when necessary.

Keywords

• timing logic analyzer
• stimulus generator
• programmable logic analyzer using Internet