High-bandwidth coupling circuit design for PLC applications on SWER networks: From design to production

Abstract

This paper proposes a novel receiver signal-conditioning circuit for Powerline Carrier (PLC) applications in medium-voltage, Single-Wire Earth Return (SWER) networks. The primary aim is to achieve increased bandwidth by lowering the frequency cut-off and leveraging the integrated drain-coil of the coupling capacitor to reduce insertion loss while maintaining signal integrity. The design introduces a flexible trade-off between bandwidth expansion and loss minimization, critical for cost-effectively enhancing communication in complex network environments. Results attested to the feasibility of extending signal reception down to 9 kHz, potentially unlocking previously inaccessible low path-loss areas within the CENELEC-A band. When all stages are engaged, the transmission bandwidth ranges from 27 kHz to 440 kHz for an adjustable insertion loss in the -50 dB to + 0 dB range. Field testing of the design resulted in an SNR greater than 0 dB for 99.99 % of the time, with 98.29 % of measured SNR falling in the 20 dB to 40 dB SNR range. The frequency range, flexibility, cost, and quantitative outcomes assert the effectiveness and reliability of the proposed solution in real SWER network conditions.

Keywords

• Powerline carrier
• Coupling circuit
• Single-wire earth return
• Medium voltage
• CENELEC-A band