Discrete-level memristive circuits for HTM-based spatiotemporal data classification system

Abstract

The authors propose a discrete-level memristive memory design for analogue data processing in hardware implementations of hierarchical temporal memory (HTM). In this study, memristors were set to ternary and quaternary states in a sub-cell by application of different write voltage levels through a resistive network configuration. Simulations of the proposed circuit show that the highest number of discrete output levels of the memory was achieved using quaternary logic. However overall, using the same number of sub-cells and ternary logic exhibits the lowest relative error rate. For data classification purposes, the proposed discrete-level memristive cells are incorporated into the TM of HTM architecture, and its hardware circuit is presented for pattern recognition. They report improved results of face recognition using AR, ORL and UFI databases, and TIMIT database for speech recognition. These results are compared with the earlier design of HTM having only the spatial pooler (SP). Accuracy of the HTM architecture incorporating both SP and TM with discrete-level memristive cells for face recognition increased from 76.5 to 83.5% for AR database and speech recognition accuracy is improved from 73.3 to 93.3%.

Keywords

• pattern classification
• memristor circuits
• memory architecture
• memristors
• discrete-level memristive circuits
• HTM-based spatiotemporal data classification system
• discrete-level memristive memory design
• analogue data processing
• hardware implementations
• hierarchical temporal memory
• quaternary states
• write voltage levels
• resistive network configuration
• quaternary logic
• discrete-level memristive cells
• HTM architecture
• hardware circuit
• pattern recognition
• face recognition
• speech recognition
• spatial pooler