Microsystems & Nanoengineering (May 2023)

Highly conformable chip-in-foil implants for neural applications

  • Thomas Stieglitz,
  • Calogero Gueli,
  • Julien Martens,
  • Niklas Floto,
  • Max Eickenscheidt,
  • Markus Sporer,
  • Maurits Ortmanns

DOI
https://doi.org/10.1038/s41378-023-00527-x
Journal volume & issue
Vol. 9, no. 1
pp. 1 – 13

Abstract

Read online

Abstract Demands for neural interfaces around functionality, high spatial resolution, and longevity have recently increased. These requirements can be met with sophisticated silicon-based integrated circuits. Embedding miniaturized dice in flexible polymer substrates significantly improves their adaptation to the mechanical environment in the body, thus improving the systems’ structural biocompatibility and ability to cover larger areas of the brain. This work addresses the main challenges in developing a hybrid chip-in-foil neural implant. Assessments considered (1) the mechanical compliance to the recipient tissue that allows a long-term application and (2) the suitable design that allows the implant’s scaling and modular adaptation of chip arrangement. Finite element model studies were performed to identify design rules regarding die geometry, interconnect routing, and positions for contact pads on dice. Providing edge fillets in the die base shape proved an effective measure to improve die-substrate integrity and increase the area available for contact pads. Furthermore, routing of interconnects in the immediate vicinity of die corners should be avoided, as the substrate in these areas is prone to mechanical stress concentration. Contact pads on dice should be placed with a clearance from the die rim to avoid delamination when the implant conforms to a curvilinear body. A microfabrication process was developed to transfer, align, and electrically interconnect multiple dice into conformable polyimide-based substrates. The process enabled arbitrary die shape and size over independent target positions on the conformable substrate based on the die position on the fabrication wafer.

Keywords