Design and simulation of high linearity CMOS analog multiplier

Abstract

A high linearity CMOS analog multiplier is designed and simulated. The input signal is preprocessed by active attenuator and the CMOS Gilbert multiplier is used for multiplication of the signal, and the bias circuit is designed meanwhile. When the supply voltage is ±1.8 V and the input range is ±0.6 V, the output range is less than ±25 mV and good linearity of the analog multiplier is obtained using optimized characteristics of transistors. The frequency doubling character of the analog multiplier is favorable since the -3 dB bandwidth of the analog multiplier is 181 MHz. Moreover, the temperature characteristic of multiplier is simulated and the layout of multiplier is designed optimally，and the relationship between linearity and output amplitude is discussed. The linearity of the multiplier during wider input range proposed herein is higher than that in the references.

Keywords

• analog multiplier
• cmos gilbert unit
• active attenuator
• high linearity