Design and Analysis of 0.5-<inline-formula> <tex-math notation="LaTeX">$f_{\mathrm{T}}$ </tex-math></inline-formula> Bandwidth THAs With Resolution Enhancement Techniques in 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math></inline-formula>m SiGe Process

Abstract

This paper presents the design and analysis of microwave and millimeter-wave (MMW) high-linear track-and-hold amplifiers (THAs) for high-speed data conversion systems. The silicon germanium (SiGe) process utilized in the proposed circuits is analyzed in detail and its several merits are demonstrated, including operating speed, linearity, and resolution. Bandwidth extension techniques, such as peaking, Darlington, and distributed topologies, are adopted to further enhance the operating speed of the proposed THAs up to a 0.5-unity current gain frequency (fT) of the transistor. The switched emitter-follower (SEF) as well as the switched capacitor (SC) track-and-hold (T/H) stages are modified using pedestal error reduction techniques, including a cascode stage and differential cancellation, to further enhance the overall resolution of the THAs. The proposed cascoded SEF-based T/H circuit with a modified Darlington-based input buffer has a track-mode bandwidth of up to 0.5-fT, a maximum spurious-free dynamic range (SFDR) of 45.1 dBc, and dc power consumption of 94.3 mW. Moreover, the proposed differential cancellation SC-based T/H circuit with an input buffer based on the distributed bandwidth extension technique exhibits an operating speed of up to 0.32-fT, an SFDR of 47.9 dBc, and dc power consumption of 180.1 mW. Both proposed THAs are suitable for low-power, high-speed MMW conversion systems without incurring a high cost. Moreover, by using the proposed design methodology, a sampling rate up to tens of gigahertz can be easily achieved with time-interleaved architecture.

Keywords

• CMOS/SiGe RFIC
• microwave integrated circuits (ICs)
• mixed signal design
• high-speed analog IC design
• sampling circuits