Ultra Sensitive PIN-Diode Receiver Utilizing Photocurrent Integration on a Parasitic Capacitance

Abstract

This work presents a highly sensitive monolithic optical receiver in $\mathrm {0.35~\mu m}$ CMOS. The integrator-based frontend employs periodic photocurrent integration on a parasitic capacitance in combination with an ultra-low-capacitance PIN photodiode. This results in a small effective integration capacitance, and thus a high input-charge-to-output-voltage conversion ratio. Interfering parasitic phenomena that had to be dealt with in the frontend are clock-feedthrough, reset settling time and mismatch. The PIN-diode itself was investigated in terms of spectral responsivity (0.32 A/W at 642 nm), capacitance (3.2 fF for $|V_{\mathrm {bias}}|\gt {\mathrm {4~V}}$ ) and bandwidth (1.7 GHz for $|V_{\mathrm {bias}}|\gt {\mathrm {10~V}}$ ). The BER of the receiver was characterized using correlated double sampling in post-processing. The resulting sensitivity of −52.32 dBm leads to a distance of 18.36 dB to the quantum limit at 100 Mb/s, 642 nm and $\mathrm {BER}=2\cdot 10^{-3}$ .

Keywords

• Capacitive transimpedance amplifier
• CMOS
• high sensitivity
• integrate and dump
• optical receiver
• PIN-diode