A Low-Overhead and High-Security Scan Design Based on Scan Obfuscation

Abstract

Scan-based side-channel attacks have been proven to be popular attack methods against cryptographic chips. In these attacks, attackers can use scan chains inside a chip to obtain internal sensitive information of the chip, such as crypto key or other secret data. To counteract scan-based side-channel attacks, various secure strategies have been put forward by researchers, but they generally exist some flaws. In this paper, we propose a low overhead secure scan design based on scan obfuscation. In this method, to increase the security of the design, we insert a set of fuse-antifuse cells (CF) controlled by the obfuscation key between the scan flip flops (SFF) and add a controller at the scan-out port. The undisturbed scan test can be launched only when both the correct test key and obfuscation key are delivered. Simulation results and theoretical analysis show that the scheme effectively thwarts scan-based attacks while maintaining minimal area overhead and high testability. In the case of a pipelined AES circuit, with a total test key and obfuscation key length of 128, the area overhead is as low as 0.07%, and the probability of a successful brute-force attack is only $2.9\times 10 ^{-39}$ .

Keywords

• Cryptographic chips
• design for testability
• scan obfuscation
• scan-based side-channel attacks