Design of a Low Power CMOS Inverter with the VBB Stack Approach

Abstract

Due to the exponential advancement in nanotechnology devices, low energy consumption has become a significant concern of researchers and VLSI designers. In this paper, the Variable body bias (VBB) and the stack approach are used simultaneously to reduce the leakage power of a CMOS inverter in standby mode. This new technique is called the VBB stack approach. The simulations have been conducted on the LT spice simulator. The power evaluation has been determined and compared between the conventional approach, the stack approach, and the VBB stack approach. The results have demonstrated the performance of the VBB stack approach. The power consumption in the VBB stack approach has decreased by 23% compared to the conventional approach and by 10% compared to the stack approach.

Keywords

• cmos inverter
• vlsi
• power dissipation
• leakage current
• low power
• vbb stack approach