A 919 MHz—923 MHz, 21 dBm CMOS Power Amplifier With Bias Modulation Linearization Technique Achieving PAE of 29% for LoRa Application

Abstract

This paper presents a bias modulation linearization technique for a 919 MHz −923 MHz CMOS power amplifier which employs driver voltage modulation and main amplifier split bias. Through the proposed linearization technique, it is observed that the peak third-order intercept point (OIP3) across the output power is shifting according to the bias conditions of the split-bias power amplifier (SBPA). The third-order transconductance ( $\text{g}_{\mathrm {m3}}$ ) terms are suppressed at the output by phase cancellation achieved by optimization of the bias voltages of the PA. A high dynamic range bias circuit is integrated at the driver and split main to enhance the linearity of the CMOS PA, eradicating the need for pre-distortion linearizers. The two-stage SBPA is designed and fabricated in a 180 nm CMOS process with six-metal layers and a chip size of $1.820\times1.771$ mm2 to operate at the supply voltage of 3.3 V. The bias voltages of both driver and split main stages are varied from 0 V to 2.0 V with a linear step size of 0.2 V. The proposed SBPA delivers a saturated output power (Pout) of 27 dBm with maximum power-added efficiency (PAE) of 44.4% and peak OIP3 of 39 dBm. A maximum linear Pout of 21 dBm with 29% PAE is achieved at an adjacent channel leakage ratio (ACLR) of −30 dBc and 4% error vector magnitude (EVM), satisfying the LoRa specifications.

Keywords

• Adjacent channel leakage ratio (ACLR)
• bias circuit
• complementary metal-oxide-semiconductor (CMOS)
• error vector magnitude (EVM)
• intermodulation distortion (IMD)
• long-range (LoRa)