Design of carrier tracking loop for Beidou receiver based on SoC FPGA

Abstract

In order to realize the high real-time, miniaturization and low power consumption of Beidou satellite navigation receiver, a design scheme of carrier tracking loop based on SoC FPGA is proposed. Through the analysis of FLL and PLL, and using SOPC technology, the carrier tracking loop based on SoC FPGA is realized, and the carrier can be completely stripped inside the FPGA. The test results show that the scheme can realize fast and accurate tracking of carrier signals, and has good real-time and application value.

Keywords

• Beidou satellite navigation receiver; carrier tracking loop; SoC FPGA