IEEE Access (Jan 2025)
A Study on the Performance Evaluation of F-Type Multilevel Inverters Employing Phase Disposition Carrier PWM Schemes
Abstract
This research presents a three-phase, three-level F-type inverter utilizing a four switch per leg and a DC link. The proposed structure necessitates less power components than traditional three-level inverter topologies, hence reducing switching stress and loss as thereby decreasing the topology cost. The suggested inverter employs a carrier-based pulse width modulation (PWM) technique, including Sine PWM, Sixty-Degree PWM, and Switching Frequency Optimal (SFO) PWM, to achieve the necessary output voltage. The inverter operates with various amplitude and frequency modulation indices (ma, m $_{\mathrm {f}}$ ), and its performance is evaluated based on total harmonic distortion (THD), fundamental output voltage, inverter losses, and efficiency. To demonstrate the efficacy of the proposed configuration, a 400 W prototype of the inverter is developed, and empirical findings are provided. The suggested inverter demonstrates exceptional performance with a modulation index of m $_{\mathrm {a}}=0.9$ and m $_{\mathrm {f}}=100$ under SFO PWM, enabling improved THD performance, increased output voltage, and greater efficiency. As the switching frequency increases, a greater portion of the harmonic spectrum shifts away from the fundamental frequency, so assuring that the SFO PWM technique requires reduced filter size.
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