Fault-tolerant method for anti-SEU of embedded system based on dual-core processor

Abstract

The development of space applications based on commercial system on chip (SOC) FPGA devices has become an important direction for the development of aerospace technology, but single event upsets (SEUs) in space is a difficult problem for commercial SOC FPGAs for space applications. This article presents an anti-anti method for ARM processors in SOC FPGA. This method makes full use of the hardware resources of dual-core ARM in SoC FPGA and improves the system's anti-SEU capability through dual-core mutual-check and recovery mechanisms. At the same time, the data stream and control flow fault tolerant are used to improve the anti-SEU capability within the processor. Error detection and correction (EDAC) and triple modular redundancy (TMR) are used to improve anti-SEU capability of the data flow. A two-level watchdog and ARM exception handling are used to achieve the anti-SEU capability of the control flow. Experimental results show that the two-level fault-tolerance mechanism proposed here improves the system's anti-SEU capability without adding additional hardware resources. This method is currently carrying out satellite-borne ground application verification.

Keywords

• error detection
• radiation hardening (electronics)
• fault tolerant computing
• field programmable gate arrays
• embedded systems
• microprocessor chips
• system-on-chip
• redundancy
• fault-tolerant method
• embedded system
• dual-core processor
• arm processors
• dual-core arm
• soc fpga
• dual-core mutual-check
• control flow
• triple modular redundancy
• two-level watchdog
• two-level fault-tolerance mechanism
• antiseu capability
• antianti method