A timing estimation algorithm for dPMR receiver based on FPGA and its implementation

Abstract

The accuracy of symbol timing synchronization has a great impact on the demodulation performance of digital communication systems. The dPMR communication system requires the symbol synchronization of the receiver to have fast acquisition and good tracking performance. A timing estimation algorithm is proposed for this requirement. The algorithm combines the advantages of preamble timing algorithm and digital square filtering algorithm. Firstly, when the preamble of the burst information is captured, the preamble timing algorithm is used to implement high-precision fast timing estimation. Then, a digital square filtering algorithm is used to implement tracking correction for timing estimation at intervals of 384 symbols. At the same time, a simple FPGA implementation scheme is proposed. Compared with the classical matching filter timing algorithm based on synchronous waveform, it not only improves the demodulation performance of the receiver but also saves hardware resources.

Keywords

• timing estimation
• fast acquisition
• timing tracking
• FPGA