Design and evaluation of an efficient parity-preserving reversible QCA gate with online testability

Abstract

The current monolithic integrated circuits revolution has been growing over past few decades, but the VLSI industry faces problems in the domain of short channel effect, device density, and scaling along with power consumption. Hence research is a need to investigate alternative nanoelectronics technology such as Quantum-dot cellular automata (QCA). This paper presents a novel reversible gate with a parity-preserving property realized using QCA technology. Results demonstrate that the proposed gate is more efficient compared to the existing parity-preserving reversible gate designs regarding the area, delay, and power consumption. To facilitate online fault detection of the proposed gate, two new reversible parity generator and parity checker circuits are proposed. The proposed even parity generator succeeded in achieving 62.5% cell count, and 23.07% area from prior works. These two circuits are designed using a new ultra-efficient exclusive-OR (XOR) gate, designed with only 11 cells with an area of 0.02 μm2. We also present an efficient fault-tolerant reversible D-latch using the proposed gate. The QCADesigner and HDLQ tools are used for designing the QCA layouts and for the functional verification of the proposed circuits, respectively. Energy dissipation analysis of the proposed gate is performed using the QCAPro simulation tool.

Keywords

• quantum-dot cellular automata
• fault-tolerant
• reversible logic
• xor gate
• qcadesigner
• qcapro
• verilog hdl
• hdlq
• logic gate
• nanotechnology