Design and Application of Memristive Balanced Ternary Univariate Logic Circuit

Abstract

This paper proposes a unique memristor-based design scheme for a balanced ternary digital logic circuit. First, a design method of a single-variable logic function circuit is proposed. Then, by combining with a balanced ternary multiplexer, some common application-type combinational logic circuits are proposed, including a balanced ternary half adder, multiplier and numerical comparator. The above circuits are all simulated and verified in LTSpice, which demonstrate the feasibility of the proposed scheme.

Keywords

• memristor
• balanced ternary
• univariate logic
• combinational logic circuit