Sub-nanosecond Gating of Large CMOS Imagers

Abstract

Ultra-fast gating of large array imagers can be quite challenging to implement due to the distributed RC (Resistance Capacitance) nature of the metal wires used in all ICs (Integrated Circuits) for electrical connections. For the transmission of a signal across a long path, the metal line reduces the electrical bandwidth and adds a delay. The behavior of these lines has been modeled and a new solution is presented to circumvent these limitations. In this paper, we present an edge-based approach to the gating circuitry that allows sub nanosecond gating with a very low skew across the whole imager. Simulation data shows that our solution is an efficient way of reducing the effect of the distributed RC line delay with a small penalty on surface area and consumption.

Keywords

• SPAD
• Ultra-fast gating
• Edge-triggered
• Fast pulse
• Skewless.