Self-Checking Hardware Design for Montgomery Exponentiation-Based Cryptography

Abstract

Montgomery exponentiation is widely used for public-key-based cryptography systems. The current state-of-the-art designs for this algorithm are well-analyzed in terms of hardware overhead but are not investigated for faults caused by physical attacks. This paper presents a self-checking hardware design for the Montgomery Multiplier (MM), which can counter multiple faults simultaneously. The proposed 64-bit self-checking MM approach with a distributed fault prognosis mechanism requires only 43.5% area and 10.9% power overhead as compared to the non-self-checking design. Moreover, a novel self-checking parity prediction approach is proposed for carry save adder, which can be used in cases where it is used alone inside a loop.

Keywords

• Montgomery exponentiation
• fault localization
• self-checking adder
• parity prediction