Design of IP Core of Signal Generator of Pseudo-random Sequence Based on Nios II

Abstract

The paper put forward a design method of IP core of signal generator of pseudo-random sequence according to Avalon bus specification of Nios II embedded system, and introduced hardware and software designs of the IP core in details. The method uses collaborative design of software and hardware of custom component to achieve IP core design of signal generator of pseudo-random sequence with adjusted code length and order. Its feasibility and correctness were proved in design of controlled vibrating signal generator.

Keywords

• pseudo-random sequence, signal generator, nios ii, sopc builder, avalon bus, ip core