A radix‐8 modulo 2n multiplier using area and power‐optimized hard multiple generator

Abstract

Abstract The moduli 2n multiplier plays a vital role in the design of a residue number system processor. When the radix‐8 booth‐encoded technique is adopted to design this kind of multipliers, the hard multiple generator is crucial in terms of area, power, and delay. This paper presents an area and power optimization technique for this kind of generators and its implementation in modulo 2n multiplier to improve the performance. The proposed hard multiplier generator (HMG) uses only ⌈log2n⌉‐2 prefix levels and (n−6)⌈log2n⌉−(⌈log2n⌉−1)2⌈log2n⌉2 total prefix operators. The synthesis of the proposed architectures is done using the Cadence tool at Generic Process design Kit‐45 nm technology. The post‐synthesis result of HMG shows 20.27%–36.57%, 2.43%–18.41% saving in area and power, respectively, while the post‐layout result of HMG shows 20.01%–35.26% and 1.33%–29.44% saving in area and power, respectively. The post‐layout result of modulo 2nmultiplier using optimized HMG shows 7.88%–10.04%, 7.87%–12.50%, 3.09%–11.29%, and 3.11%–8.79% saving in area, power, switching energy and Area delay product, respectively.

Keywords

• integrated circuit layout
• logic design
• microprocessor chips
• multiplying circuits
• residue number systems