IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (Jan 2020)

Special Topic on Tunnel Field-Effect Transistors

  • Uygar E. Avci

DOI
https://doi.org/10.1109/JXCDC.2021.3053416
Journal volume & issue
Vol. 6, no. 2
pp. ii – ii

Abstract

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The tunneling field-effect transistor (T-FET) is considered a future transistor option due to its steep-slope prospects and the resulting advantages in operating at low supply voltage ( $V_{\mathrm {DD}}$ ). Reducing supply voltage while keeping a low leakage current and a reasonably high ON-current is critical for minimizing energy consumption and continue Moore’s law by helping with energy efficiency of computing. The thermal limit of the MOSFET transistor subthreshold swing (SS) restricts lowering its threshold voltage ( $V_{t}$ ), causing significant performance degradation at low $V_{\mathrm {DD}}$ . A T-FET’s SS is not limited by this thermal tail and may perform better at low $V_{\mathrm {DD}}$ .