Highly Efficient, Zero-Skew, Integrated Clock Distribution Networks Using Salphasic Principles

Abstract

The design of highly efficient clock distributions for integrated circuits is an active topic of research as there will never be a single solution for all systems. For high performance digital or mixed-signal circuits, achieving zero-skew clock over large areas usually comes with high costs in power requirements and design complexity. The present paper shows an overview of a recently proposed technique for ICs - on-die salphasic clock distribution, introduced by the author for CMOS processes. Initially reported in literature for rack-systems, the present paper shows that further refinements are needed for the concept to be applicable on a silicon die. Based on the formation of a standing wave (intrinsically presenting extended in-phase regions) with a voltage peak at the input (creating a no-load condition), it is shown that any IC implementation must use transmission lines loss compensation techniques to maintain the proper standing wave configuration. Furthermore, the paper shows theoretical solutions and describes practical on-die techniques for pseudo-spherical bidimensional surfaces, which, with the already reported orthogonal and pseudo-orthogonal structures, can be used to distribute with minimal power requirements a zero-skew clock signal, over large silicon areas.

Keywords

• bi-dimensional clock distribution
• loss compensation
• salphasic
• standing wave
• zero-skew