Efficient Hardware Realization of SC Polar Decoders Using Compound Pipelined Processing Units and Auxiliary Registers

Abstract

Polar codes have garnered substantial research attention due to their impressive performance characteristics and have found applications in recent technologies, including 5G New Radio (NR) systems, Internet of Things (IoT) communications, and cyber-physical systems that utilize sensor and actuator networks. However, the existing SC decoders suffer from lengthy processing latencies due to their sequential processing steps, thereby restricting the practical applicability of polar codes. To address this latency issue, this paper introduces a Compound Pipeline Processing Unit (CPPU) and its simplified counterpart, a crucial step in realizing tree-level compound pipelining. In contrast to sequential circuitry, the previously described combinational architecture lacks internal storage elements, with the clock period defined by the longest path delay. This strategy conserves hardware resources by avoiding memory usage, but it inevitably decelerates the decoder’s performance. Notably, implementation results underline the efficiency of the proposed CPPU-based SC polar decoder using a fully unrolled encoder and decoder on the targeted platform of a Virtex UltraScale - XCVU190 Field Programmable Gate Array (FPGA), using a parametric approach in the Very High-Speed Integrated Circuit Hardware Description Language (VHDL). The assessment of error-correction performance involves examining various combinations of integral and fractional bits in LLR quantized representations. This approach achieves a throughput of about 2672 Mbps, accompanied by a substantial reduction of 17% in Lookup Table (LUT) usage. Furthermore, the decoder’s speed is enhanced by approximately 17.34% for a code length of 128 bits and LLR quantization of 5 bits.

Keywords

• Polar codes implementations
• compound-logic pipeline processing
• latency reduction
• simplified non-statistical LLR metric