Design of Novel and Low Cost Triple-node Upset Self-recoverable Latch

Abstract

With the development of semiconductor technology, the size of transistors continues to shrink. In complex radiation environments in aerospace and other fields, small-sized circuits are more prone to soft error (SE). Currently, single-node upset (SNU), double-node upset (DNU) and triple-node upset (TNU) caused by SE are relatively common. TNU’s solution is not yet fully mature. A novel and low-cost TNU self-recoverable latch (named NLCTNURL) was designed which is resistant to harsh radiation effects. When analyzing circuit resiliency, a double-exponential current source is used to simulate the flipping behavior of a node’s stored value when an error occurs. Simulation results show that the latch has full TNU self-recovery. A comparative analysis was conducted on seven latches related to TNU. Besides, a comprehensive index combining delay, power, area and self-recovery—DPAN index was proposed, and all eight types of latches from the perspectives of delay, power, area, and DPAN index were analyzed and compared. The simulation results show that compared with the latches LCTNURL and TNURL which can also achieve TNU self-recoverable, NLCTNURL is reduced by 68.23% and 57.46% respectively from the perspective of delay. From the perspective of power, NLCTNURL is reduced by 72.84% and 74.19%, respectively. From the area perspective, NLCTNURL is reduced by about 28.57% and 53.13%, respectively. From the DPAN index perspective, NLCTNURL is reduced by about 93.12% and 97.31%. The simulation results show that the delay and power stability of the circuit are very high no matter in different temperatures or operating voltages.

Keywords

• circuit reliability
• latch design
• self-recoverability
• soft error
• radiation hardening
• triple-node upset