New Design-methodology of High-performance TDC on a Low Cost FPGA Targets

Abstract

This work aims to introduce a design methodology of Time-to-Digital Converters (TDCs) on low cost Field-Programmable Gate Array (FPGA) targets. First, the paper illustrates how to take advantage of the presence of carry chains in elementary logic elements of the FPGA in order to enhance the TDC resolution. Then, it describes how to use the Chip Planner tool to place the partitions composing the system in user specified physical regions. This allows the placement of TDC partitions so that the routing paths are constrained. As a result, the user controls the propagation delay effectively through the connection network. The paper ends by applying the presented methodology to a case study showing the design and implementation of high resolution TDC dedicated to time correlated single photon counting system. The resolution of 42 ps as well as the INL, DNL and mean Jitter values (22 ps rms, 13 ps rms and 26 ps rms, respectively) obtained using a low cost FPGA target Cyclone family are very promising and suitable for a large amount of fast applications.

Keywords

• Time-to-digital converter
• FPGA
• Chip planner
• Carry chain logic
• Time correlated single photon counting.