Implementation of Efficient XOR Arbiter PUF on FPGA With Enhanced Uniqueness and Security

Abstract

Physically unclonable functions (PUFs) are recently utilized as a promising security solution for authentication and identification of internet of things (IoT) devices. In this article, we present an efficient implementation of XOR Arbiter PUF (XOR APUF) on field-programmable gate arrays (FPGAs). In our work, we incorporated concept of discrete programmable delays logic (PDL) configurations, the obfuscated challenges and temporal majority voting (TMV) before the XOR operation concurrently to enhance uniqueness and security. The derived design has been verified on 25 Xilinx Artix-7 FPGAs and the results are promising with uniqueness of 48.69%, uniformity 50.73% and reliability 99.41%, which significantly improves over previous work into XOR APUF designs. In addition, we also investigate modeling attack resistance of the proposed design against various modelling attacks and the security analysis show that the proposed PUF has lower prediction rate (<65%) when compared to the previous XOR APUF designs.

Keywords

• Physical unclonable functions (PUFs)
• Internet of Things (IoT)
• programmable delays line (PDL)
• FPGA
• XOR arbiter PUF (XOR APUF)