Bitline Charge Sharing Suppressed Bitline and Cell Supply Collapse Assists for Energy-Efficient 6T SRAM

Abstract

This paper proposes a bitline charge sharing suppressed bitline read assist (BCS RA) and a cell supply collapse write assist (BCS WA). The proposed BCS RA suppresses the bitline (BL) voltage to half of the supply voltage ( $\text{V}_{\mathrm {DD}}$ ) using the charge sharing BL precharger for improving read stability and energy efficiency. In the proposed BCS WA, the charge on cell $\text{V}_{\mathrm {DD}}$ (CV $_{\mathrm {DD}}$ ) is shared with that on the BL precharged to half- $\text{V}_{\mathrm {DD}}$ by the charge sharing write driver, which causes the collapse in CVDD. In cells with poor writability, CVDD can be collapsed more by the self-collapse paths when the write operation is performed. Thus, the BCS WA improves writability and reduces write energy consumption. The simulation results using 22-nm FinFET technology show that static random access memory (SRAM) using BCS RA and WA consumes much less read and write energy than SRAMs using state-of-the-art assists while achieving a comparable minimum operating $\text{V}_{\mathrm {DD}}$ to SRAMs using state-of-the-art assists. Even compared to the SRAM without assists, the read and write energy consumption is reduced by 31% and 26%, respectively.

Keywords

• FinFET SRAM
• read assist
• write assist
• VMIN improvement
• energy-efficient read and write operations