A Logistic Map Runge Kutta-4 Solution for FPGA Using Fixed Point Representation

Abstract

Logistic map can show simple chaotic behavior pattern. Chaotic patterns with their irregularity and unpredictability properties are often used for random number generation and encryption. Hence, simple implementation of logistic map with chaotic behaviour is studied on how to solve differential equations with Runge Kutta Order-4 on FPGA and compared with floating point and fixed point representations. In the study, the logistic map equation is modelled with Verilog hardware description language and system is simulated using ModelSim and MATLAB environment. This paper reveals fundemental chaotic pattern implementation using logistic map to obtain unpredictable resuts on FPGA using xed point number representation. Experimental results confirm both Verilog and MATLAB implementation produce same results. The results obtained from system in different generations can be converted to fixed point numeric values with an error margin. Error margin changes based on bit-length of fixed point number representation design.

Keywords

• chaos
• logistic map
• fpga
• verilog