Embedding delay‐based physical unclonable functions in networks‐on‐chip

Abstract

Abstract Physical unclonable functions (PUFs) are emerging as security primitives by exploiting the intrinsic device features in various hardware security solutions. This article proposes a mechanism to embed delay‐based PUFs, namely arbiter PUF and ring‐oscillator PUF, in the network‐on‐chip (NoC) architecture. These embedded PUFs are constructed by reusing already available hardware resources in NoCs, such as the crossbar switches. Pass transistors, which work as control components, have been added into the delay paths. A 5‐port NoC router has been considered and the corresponding 5 × 5 crossbar switches have been analysed after obtaining a suitable layout to embed the delay‐based PUFs. The embedded PUFs have been qualitatively analysed for their robustness against variations in supply‐voltage. Furthermore, a qualitative study on generating secret keys from the embedded PUFs has been presented. A PUF‐specific layout has been considered for implementing the NoC crossbar switches, and for extracting the RC interconnection delays. Monte Carlo simulations have been performed to evaluate the quality metrics of the proposed embedded PUFs for a 64‐bit response. Area overheads incurred for realizing the proposed embedded PUFs have been found to be 6.38% and 2.68%, for arbiter PUF and ring‐oscillator PUF, respectively. Furthermore, by incorporating the pass transistors in the control components, the reliability metrics have been found to be reasonably improved over traditional constructions of the arbiter and the ring‐oscillator PUFs.

Keywords

• integrated circuit design
• integrated circuit interconnections
• integrated circuit reliability
• logic design
• Monte Carlo methods
• network‐on‐chip