Address Translation in a Compositional Microprogram Control Unit

Abstract

Introduction. Digital systems consist of combinational and sequential blocks. The most important sequential blocks include control units. Control unit circuits are not typical library components of CAD systems. Due to it, the designing a control unit circuit is a more labor-intensive process than implementing systems with such common blocks as registers, counters, arithmetic and logic blocks. The purpose of the article. When implementing digital systems, problems arise in optimizing their characteristics. This paper considers the problem of reducing hardware costs in the circuits of compositional microprogram control units (CMCU). The resources of FPGA (field-programmable logic array) chips are used as an element basis. The method proposed in the article is based on the adaptation of algorithms for optimizing microprogram automata circuits to the features of CMCUs. The method is aimed at converting the addresses of some microinstructions into partial inputs. Under certain conditions, this approach can significantly simplify the block of microinstruction addressing. This approach can improve the characteristics of the CMCU circuit in comparison with other known methods. The language of graph-schemes of algorithms (GSA) is used to specify the algorithm for the CMCU operating. Results. The implementation of the CMCU circuit using such FPGA chip resources as look-up table (LUT) elements and embedded memory blocks (EMB) is considered. Optimization is achieved by using the EMB redundancy at the outputs. The proposed method allows improving such basic CMCU characteristics as the chip area occupied by the CMCU circuit, the maximum operating frequency, the total number of interconnections and the power consumption. The article presents a step-by-step algorithm for synthesizing the CMCU for a given GSA. Also, it provides an example of CMCU synthesis using the proposed method. At last, the conditions of the proposed method’s applicability are shown. Conclusions. The proposed method allows reducing the number of LUT elements in the CMCU addressing circuit. This minimization does not require any additional FPGA chip resources. Reducing the number of LUT elements is achieved by using the redundancy of the EMB block outputs.

Keywords

• cmcu
• lut
• emb
• operator linear chains