Design Space Exploration of HW Accelerators and Network Infrastructure for FPGA-Based MPSoC

Abstract

Supercomputing systems are increasingly reliant on heterogeneous Multiprocessors System on-Chip (MPSoCs), merging multiple processors and hardware accelerators (HWAcc) on the same die to achieve power and performance needs. Due to CPU complication and timing closure challenges of tightly coupled design approach, the state-of-the art of HWAcc design methodology relies on coupling the processors with loosely coupled HWAccs. Loosely-coupled HWAccs can be shared or private accelerators running custom instructions to form a heterogeneous multi-processor system. Some works discussed the determination of the sharing degree of the HWAcc over the processors, however the impact of the integrated communication infrastructure is not discussed. Thus, we propose a high-level design exploration tool to select the accelerators and generate the adequate communication interconnect under performance and area constraints. Different homogeneous and heterogeneous multi-processor configurations are evaluated and compared running different signal processing benchmarks. Experimental results show the efficiency of the proposed exploration tool to rapidly explore and select the adequate architecture.

Keywords

• Multi-processor system-on-chip
• custom instructions
• shared hardware accelerator
• network communication
• high-level exploration