A modified MixColumn-InversMixColumn in AES algorithm suitable for hardware implementation using FPGA device

Abstract

This article described the Advanced Encryption Standard (AES) encryption and decryption process without using lookup tables in the MixColumns transformation and parallelizing the transformation process implemented in the Field Programmable Gate Array (FPGA) hardware. Parallelism of the hardware process conducted to the transformation of key schedule, addroundkey, subbyte and shiftrows (subshift) and mixcolumns in the first 5 rounds of the encryption process. The decryption process was parallelized in subshift transformations, both transformations were implemented at the same time. This research produced a modified AES encryption and decryption method and algorithm with the aim of minimizing the resources required for hardware implementation. The method in this article was applied to Xilinx ISE 14.7 software. The experimental results showed that the encryption process required 2,357 slice LUT's, 845 occupied slices and 26 IOB's, while the decryption process required 2,896 LUT's, 1,323 occupied slices and 26 IOB's resources. The encryption and decryption processes each took an average of 2.891 nanoseconds and 3.467 nanoseconds for every 128 bits of data. This approach leads us to obtain a component with minimum resources and enough computational speed.

Keywords

• aes
• fpga
• mixcolumns
• inversemixccolumns
• hardware implementation