Variable-Length Transfer Delay-Based Synchronization Approach for Improved Dynamic Performance in Single-Phase Inverters

Abstract

Synchronization of single-phase inverters is a challenging task due to the difficulty of deriving a rotating voltage frame, in the absence of adequate information from the other two phases. Moreover, modern standards, such as the fault ride-through (FRT) directives, require inverter-based distributed generators (IBDGs) to respond as fast as possible to grid disturbances; thus, it is necessary to rely on accurate and fast synchronization algorithms. The scope of this paper is to propose a new synchronization technique, which satisfies three important requirements: a) fast dynamic response, b) adequate double frequency rejection, c) low computational complexity. Our synchronization technique is a flexible method relying on variable-length transfer delay, which calculates network frequency by analyzing voltage angle differentials. To enhance this differentiation process and address potential discontinuities, we introduce Heaviside-based functions. Both simulations conducted in MATLAB/Simulink and experimental trials demonstrate that our proposed synchronization method outperforms the most widely adopted existing techniques in terms of dynamic response and computational efficiency. Due to its excellent dynamic performance, the proposed method can offer a stable FRT capability, with fast detection of the voltage dips and seamless resynchronization following fault clearance, all while preventing DC-link overvoltage issues.

Keywords

• Frequency locked loop
• inverter
• phase locked loop
• single-phase PLL
• synchronization