A 9-10-Bit Adjustable and Energy-Efficient Switching Scheme for Successive Approximation Register Analog-to-Digital Converter with One Least Significant Bit Common-Mode Voltage Variation
Yunfeng Hu,
Chaoyi Chen,
Lexing Hu,
Qingming Huang,
Bin Tang,
Mengsi Hu,
Bingbing Yuan,
Zhaohui Wu,
Bin Li
Affiliations
Yunfeng Hu
School of Electronics and Information Engineering, University of Electronic Science and Technology of China, Zhongshan Institute, Zhongshan 528402, China
Chaoyi Chen
School of Electronics and Information Engineering, University of Electronic Science and Technology of China, Zhongshan Institute, Zhongshan 528402, China
Lexing Hu
School of Electronics and Information Engineering, University of Electronic Science and Technology of China, Zhongshan Institute, Zhongshan 528402, China
Qingming Huang
School of Electronics and Information Engineering, University of Electronic Science and Technology of China, Zhongshan Institute, Zhongshan 528402, China
Bin Tang
School of Electronics and Information Engineering, University of Electronic Science and Technology of China, Zhongshan Institute, Zhongshan 528402, China
Mengsi Hu
School of Electronics and Information Engineering, University of Electronic Science and Technology of China, Zhongshan Institute, Zhongshan 528402, China
Bingbing Yuan
School of Electronics and Information Engineering, University of Electronic Science and Technology of China, Zhongshan Institute, Zhongshan 528402, China
Zhaohui Wu
School of Microelectronics, South China University of Technology, Guangzhou 510640, China
Bin Li
School of Microelectronics, South China University of Technology, Guangzhou 510640, China
A 9-10-bit adjustable and energy-efficient switching scheme for SAR ADC with one-LSB common-mode voltage variation is proposed. Based on capacitor-splitting technology and common-mode conversion techniques, the proposed switching scheme reduces the DAC switching energy by 96.41% compared to the conventional scheme. The low complexity and the one-LSB common-mode voltage offset of this scheme benefit from the simultaneous switching of the reference voltages of the capacitors corresponding to the positive array and the negative array throughout the entire reference voltage switching process, and the reference voltage of each capacitor in the scheme does not change more than two voltages. The post-layout result shows that the ADC achieves the 54.96 dB SNDR, the 61.73 dB SFDR, and the 0.67 μw power consumption with the 10-bit mode and the 48.33 dB SNDR, the 54.17 dB SFDR, and the 0.47 μw power consumption with the 9-bit mode in a 180 nm process with a 100 kS/s sampling frequency.
