IEEE Open Journal of the Solid-State Circuits Society (Jan 2021)

A Compact Chopper Stabilized Δ-ΔΣ Neural Readout IC With Input Impedance Boosting

  • Shiwei Wang,
  • Marco Ballini,
  • Xiaolin Yang,
  • Chutham Sawigun,
  • Jan-Willem Weijers,
  • Dwaipayan Biswas,
  • Nick Van Helleputte,
  • Carolina Mora Lopez

DOI
https://doi.org/10.1109/OJSSCS.2021.3113887
Journal volume & issue
Vol. 1
pp. 67 – 78

Abstract

Read online

This paper presents a scalable neural recording analog front-end architecture enabling simultaneous acquisition of action potentials, local field potentials, electrode DC offsets and stimulation artifacts without saturation. By combining a DC-coupled $\Delta $ - $\Delta \Sigma $ architecture with new bootstrapping and chopping schemes, the proposed readout IC achieves an area of 0.0077 mm2 per channel, an input-referred noise of 5.53 ± 0.36 $\mu \text{V}_{\mathrm{ rms}}$ in the action potential band and 2.88 ± 0.18 $\mu \text{V}_{\mathrm{ rms}}$ in the local field potential band, a dynamic range of 77 dB, an electrode-DC-offset tolerance of ±70 mV and an input impedance of 663 $\text{M}\Omega $ . To validate this neural readout architecture, we fabricated a 16-channel proof of-concept IC and validated it in an in vitro setting, demonstrating the capability to record extracellular signals even when using small, high-impedance electrodes. Because of the small area achieved, this architecture can be used to implement ultra-high-density neural probes for large-scale electrophysiology.

Keywords