Design Space Exploration of SDR Vector Processor for 5G Micro Base Stations

Abstract

This paper studies the design requirements and challenges of SDR (Software-Defined Radio) vector processors for 5G micro base stations. Pareto principle reflects the rule of “vital few and trivial many”, which states that 80% of consequences stem from 20% of causes. Since 20% of the instructions account for about 80% of the running time of the micro base station processor, it is essential to speed up the 20% instructions as the complex vector operations consuming most of the runtime. This paper proposes instruction fusion strategy and black-box acceleration strategy to speed up the kernel function of the micro base station algorithms. The experimental results show that the instruction fusion strategy can make the performance improvement ratio reach up to 17% while running the BDTI/ EEMBC benchmark, and the black-box acceleration strategy can make the performance improvement ratio reach about 5% while running the kernel of matrix inversion. In addition, our SIMD micro architecture is designed as a vector processor to eliminate the extra costs when implementing kernel micro scheduling. This paper provides a reference for the hardware implementation of 5G micro base stations with low cost and low-power consumption.

Keywords

• 5G micro base stations
• software-defined radio
• vector processor
• instruction space