REDUCING LDPC DECODER COMPLEXITY BY USING FPGA BASED ON MIN SUM ALGORITHM

Abstract

Low-Density Parity-Check (LDPC) code approaches Shannon–limit execution for twofold ‎field and long code lengths. The point of this work is to propose an LDPC calculation for Min ‎Sum (MS) deciphering and playing out its equipment execution investigation inside a proposed ‎communication framework. The MS calculation principally utilizes the base and expansion finding ‎procedure. The quantity of increases is subsequently altogether diminished, which tends to ‎decrease the execution intricacy. The consequences of the reenactment show that the proposed ‎MS interpreting calculation performs the same as the translating of the Sum-Product Algorithm ‎‎(SPA) while keeping up with the principle highlights of the MS disentangling. The further developing execution ‎by diminishing the number of stages in the deciphering system, diminishing the intricacy of the ‎implementation of the Field Programmable Gate Array (FPGA).‎

Keywords

• ldpc
• ms
• spa
• log domain.