Overview of routing algorithms for network on chip

Abstract

This paper examines routing algorithms for networks on a chip (NoC). An analysis of existing routing algorithms is provided; their limitations and areas of application are highlighted. The algorithms were evaluated taking into account the requirements of specific applications and architecture features. The results of comparing the performance of the considered algorithms are presented. Analysis and comparison of various routing algorithms for NoC are carried out taking into account critical characteristics. The main attention is paid to such routing algorithms as the deterministic XY algorithm, the model rotation algorithm, congestion-aware routing, fault-tolerant routing, Quality of Service routing, and the ant colony algorithm. It is shown that the choice of routing algorithm should be based on the specific requirements and conditions of use of the network. The importance of adapting to a variety of conditions and tasks that NoC users and developers may encounter is shown. Based on data from existing studies, an analysis of algorithms was carried out based on several key indicators: latency, throughput, adaptability, fault tolerance and implementation complexity. The strengths and weaknesses of each algorithm are identified in various use scenarios and under different network loads. It is shown that the choice of a routing algorithm should be based on the specific requirements and conditions of use of the network, as well as on the balance between performance, adaptability, fault tolerance and implementation complexity. The study contributes to the understanding of the effectiveness of various routing algorithms in NoC, providing recommendations for their selection depending on the specific application requirements and system architecture. The study contributes to a better understanding of the impact of routing algorithms on the overall performance of NoC, suggesting directions for further improvements in this area. The results of the work can be applied in the design and development of highperformance multiprocessor systems on a chip where efficient data routing between various systems components is a key factor in ensuring high performance. The importance of developing fault-tolerant routing algorithms that can ensure the continuity of system operation in the event of failures of individual components or units is emphasized. This is especially important for mission-critical applications where service continuity and reducing the risk of data loss are top priorities.

Keywords

• integrated circuits
• multicore systems
• network on a chip
• traffic patterns
• deadlock
• resource starvation
• routing algorithms
• deterministic routing algorithms
• fault-tolerant routing
• congestion-aware routing
• network efficiency