Prospects and Development of Vertical Normally-off JFETs in SiC

Abstract

This paper reviews the prospects of normally-off (N-off) JFET switch in SiC. The potential of selected vertical JFET concepts and all-JFET cascode solutions for N-off operation is analyzed using simulations. The performance of analyzed concepts is compared in terms of blocking voltage, specific on-state resistance, maximum output current density and switching performance in the temperature range from 25°C to 250°C. The main objective of the analysis is to ascertain consequences of different design and technology options for the total losses and high temperature performance of the devices.

Keywords

• JFET cascode
• normally-off
• SiC
• vertical JFET