Automatic power‐stage partitioning method for reconfigurable SC DC‐DC converters with reduced power‐cell redundancy

Abstract

Abstract This letter presents an automatic power‐stage implementation and optimization methodology for fully‐integrated reconfigurable switched‐capacitor (SC) DC‐DC converters with fine‐grained voltage conversion ratios (VCRs). The proposed technique resolves the design challenge of a simultaneous realization of full capacitance utilization, optimal sub‐cell sizing ratio, and implementation complexity reduction. It is based on the proposed partitioning algorithms and attains a significant sub‐cell number reduction, particularly for finer‐grained VCR designs, saving the power‐stage area overhead. With a given set of VCRs and hardware constraints, the proposed methodology can generate a specific power‐stage partitioning solution, including the total number and sizing ratio for the power stage sub‐cells, ensuring an optimal power‐stage conduction loss property under a given on‐chip capacitance area. The proposed methodology is applicable to both linear and binary types of SC converters. Compared with the advanced works, the proposed method realizes the number of sub‐capacitors reduction over 50% under the same VCRs. Meanwhile, over 90% of the sub‐cells can be eliminated for linear‐type SC converters with a VCR range of 10:1–2:1, theoretically.